Design Engineer (Broadcast Infrastructure & Automation)

Responsibilities

• Support end-to-end physical design implementation activities including floorplanning, placement, clock tree synthesis (CTS), routing, timing closure, and physical verification for advanced ASIC/SoC platforms used in digital media and broadcast technology environments.
• Perform block-level and top-level implementation for high-performance digital processing modules supporting media streaming, video processing, and communication systems.
• Drive timing closure activities across multi-corner multi-mode (MCMM) scenarios to achieve performance, power, and area targets.
• Analyze and resolve congestion, routing, and signal integrity issues through floorplan optimization and implementation improvements.
• Support low-power implementation methodologies including multi-voltage design, leakage optimization, and power-aware verification techniques.
• Collaborate closely with cross-functional engineering teams including architecture, RTL, verification, and system integration teams to support successful platform deployment.
• Contribute to hardware acceleration and infrastructure optimization initiatives supporting live broadcast workflows, media delivery systems, and high-throughput streaming environments.
• Support clock distribution and synchronization optimization for latency-sensitive digital processing applications.
• Participate in performance analysis and implementation tuning for scalable digital media processing platforms.
• Develop and maintain TCL/Python-based automation solutions to improve engineering productivity and streamline physical design workflows.
• Build reusable scripts, utilities, and internal engineering tools to support implementation, reporting, validation, and data analysis activities.
• Contribute to workflow optimization initiatives to improve design turnaround time, automation efficiency, and operational scalability.

Requirements

• Bachelor’s Degree in Electronics & Communication Engineering, Electrical Engineering, Computer Engineering, or related discipline.
• Minimum 4 years of hands-on industry experience in ASIC/SoC physical design and implementation flows.
• Experience working on advanced technology nodes and high-performance digital platforms is preferred.
• Strong analytical, debugging, and problem-solving capabilities.
• Ability to work effectively in collaborative and fast-paced engineering environments.
• Exposure to digital media systems, communication infrastructure, streaming technologies, or high-throughput computing platforms will be advantageous.
• Familiarity with software-integrated hardware development environments and engineering automation frameworks is preferred.
• Strong hands-on experience with Synopsys Fusion Compiler, Cadence Innovus, Synopsys PrimeTime and Cadence Conformal (LEC/CLP)
• Proficiency in TCL and Python scripting for workflow automation and engineering tool development