Design Engineer (Broadcast Silicon Infrastructure)

Responsibilities

• Develop IP-level and system-level verification environments for ASIC/SoC designs used in high-performance media processing and broadcast infrastructure platforms.
• Create detailed verification plans, functional coverage models, and validation strategies based on RTL specifications to ensure correctness of digital media processing pipelines.
• Build and maintain SystemVerilog-based testbenches using Universal Verification Methodology (UVM), including drivers, monitors, scoreboards, reference models, and checkers.
• Verify correctness of data movement, synchronization, and buffering across multi-channel video and communication pipelines used in live broadcast environments.
• Define and execute functional and code coverage closure strategies to ensure design completeness prior to silicon tape-out.
• Validate high-speed on-chip interconnect protocols including AXI3, AXI4, and APB used in high-throughput media and communication subsystems.
• Verify memory subsystems including SRAM, dual-port RAM, and FIFO architectures to ensure reliable data buffering and zero-data-loss streaming behavior.
• Validate data integrity across clock-domain crossings (CDC), multi-clock systems, and multi-voltage environments used in high-performance digital platforms.
• Debug functional mismatches, assertion failures, and protocol violations using industry-standard simulation and debugging tools.
• Analyze simulation failures, waveform behavior, and coverage gaps to identify root causes of design and implementation issues.
• Drive functional closure through systematic test development, assertion-based verification, and regression analysis.
• Ensure high confidence design sign-off through completion of coverage goals and verification metrics.
• Develop and maintain automated regression frameworks for large-scale simulation environments.
• Integrate Verification IP (VIP) components into reusable, scalable verification environments.
• Build automation scripts and flow enhancements to improve simulation efficiency and verification throughput.
• Support software-driven verification infrastructure improvements to accelerate design validation cycles and improve engineering productivity.

Requirements

• Bachelor’s Degree in Electronics & Communication Engineering (ECE), Electrical Engineering, or related discipline.
• Minimum 3+ years of industry experience in Design Verification, IP-level verification, or SoC verification.
• Strong hands-on experience in SystemVerilog, UVM, SVA and multi-voltage verification concepts
• Strong Knowledge in Scripting / productivity tools such as Shell, Python, or equivalent automation tools
• Strong Protocol Knowledge such as AXI3 / AXI4 and APB3
• Basic understanding of on-chip interconnect and memory subsystems
• Strong understanding of RTL design concepts, digital architecture, and verification closure methodologies.
• Experience in building UVM testbenches and developing reusable verification components.
• Exposure to high-performance communication systems, multimedia processing, streaming infrastructure, or data-intensive digital systems is advantageous.
• Strong analytical and debugging skills with a structured approach to problem-solving.
• Ability to work in cross-functional engineering teams in fast-paced development environments.